1. Field of the Invention
The present invention relates to a data reading circuit used in a semiconductor memory device, and in particular, to a data reading circuit for reading data conducted from a memory cell to an input/output line pair.
2. Description of the Background Art
In a semiconductor memory device, data is written into a memory cell. In such a semiconductor memory device, a data reading circuit is provided for reading data written into the memory cell. When reading the data from the memory cell, the data stored in the memory cell is conducted to a bit line pair. Then, the data is conducted to an input/output line pair from the bit line pair through a column selecting gate or the like.
The data reading circuit is connected to the input/output line pair. This data reading circuit senses and amplifies the potential difference produced at the input/output line pair corresponding to the data conducted from the memory cell, and externally outputs the read data at a level corresponding to the potential difference.
FIG. 7 is a circuit diagram of a conventional data reading circuit.
Referring to FIG. 7, this data reading circuit includes a sense amplifier 1, tri-state inverters 2 and 3, a static latch circuit 4, and a P channel MOS transistor (hereinafter referred to as PMOS transistor) 55.
Sense amplifier 1 has a pair of input nodes to which a pair of input/output lines IO and IO are connected. In addition, sense amplifier 1 receives a sense enable signal SE as a control signal.
PMOS transistor 55 for precharging is connected between a potential node N1 which receives a power supply potential Vdd and a node N3 which serves as an output node of sense amplifier 1. This PMOS transistor 55 receives sense enable signal SE at its gate electrode.
Tri-state inverter 2 is an inverter for amplifying the signal amplitude. This tri-state inverter 2 is supplied with a signal output from sense amplifier 1. Also, tri-state inverter 2 receives sense enable signal SE as a control signal.
Static latch circuit 4 includes inverters 41 and 42 forming a latch circuit in which an input terminal of one inverter is connected to an output terminal of the other inverter and an output terminal of one inverter is connected to an input terminal of the other inverter. In this static latch circuit 4, a node between the output terminal of inverter 42 and the input terminal of inverter 41 is connected to a node N4 which serves as an output node of tri-state inverter 2.
Tri-state inverter 3 is an inverter for output. This tri-state inverter 3 is supplied with a signal output from tri-state inverter 2. In addition, tri-state inverter 3 receives an output enable signal OE as a control signal. Output signal of tri-state inverter 3 is supplied to a node N5 which serves as an output node.
Operation of the data reading circuit shown in FIG. 7 will now be described.
When sense enable signal SE is at L level, sense amplifier 1 and tri-state inverter 2 would both be in an inactive state (high impedance state), and at the same time, PMOS transistor 55 is rendered conductive.
When PMOS transistor 55 is rendered conductive, power supply potential Vdd is supplied to node N3. Thus, when sense amplifier 1 is inactive, node N3 is precharged to the level of power supply potential Vdd. This precharging is performed so as to improve the access rate.
Thereafter, when sense enable signal SE attains H level, both of sense amplifier 1 and tri-state inverter 2 are made active, and at the same time, PMOS transistor 55 is rendered non-conductive. In this case, potential difference between input/output line pair IO and IO is sensed and amplified at sense amplifier 1. As a result, sense amplifier 1 outputs a signal having a level corresponding to the state of signals (the state of potential difference) at input/output line pair IO and IO.
In this case, tri-state inverter 2 would invert, amplify, and output the signal input thereto. Here, the amplitude of the input signal is amplified.
Static latch circuit 4 latches the output signal of tri-state inverter 2 by inverters 41 and 42. Thus, potential at node N4 is maintained by static latch circuit 4.
Tri-state inverter 3 is activated in response to output enable signal OE. When activated, tri-state inverter 3 inverts the input signal and outputs the inverted signal.
Operation in which two data are successively read (hereinafter referred to as successive reading operation) in the data reading circuit of FIG. 7 will be described next.
There are four types of successive reading operations. In a first successive reading operation, data is read in the order of H level-H level. In a second successive reading operation, data is read in the order of H level-L level. In a third successive reading operation, data is read in the order of L level-L level. In a fourth successive reading operation, data is read in the order of L level-H level.
FIG. 8 is a timing chart for the successive reading operations in the data reading circuit shown in FIG. 7.
This FIG. 8 shows an example in which the first to fourth successive reading operations are performed continuously. In addition, sense enable signal SE, potential of node N3, potential of node N4 and potential of node N5 in each successive reading operation are shown, respectively. When these successive reading operations are performed, output enable signal OE is fixed at H level.
To begin with, the first successive reading operation will be described. First, in an initial sense cycle (a cycle in which a sensing operation is performed) SC, data at H level (the level of power supply potential Vdd) is read out.
Then, node N3 is precharged to H level in a precharge cycle (a cycle in which precharging is performed), and in addition, data at H level is read in the next sense cycle SC.
In this situation, since node N3 continues to be at H level, node N4 continues to be at H level. Accordingly, there is no problem caused in the access time in the case of this first successive operation.
Next, the second successive reading operation will be described. Here, data at H level is read in an initial sense cycle SC. Thereafter, node N3 is precharged to H level in a precharge cycle PC, and data at L level (the level of ground potential gnd) is read in the next sense cycle SC.
In this case, since L level is read after the precharging of node N3 to H level in the precharge cycle PC, it takes a long time before the level of node N3 is turned to H level. Accordingly, rate of access in access time Tac3 is made slower.
Furthermore, in the operation of tri-state inverter 2, it takes a long time before the signal level reaches a logical threshold value when the input amplitude is large. Thus, in the second successive reading operation, the access is further slowed down.
The third successive reading operation will be described next. Here, an L level data is read in an initial sense cycle SC. Then, in a precharge cycle PC, node N3 is precharged to H level, and data of L level is read in the next sense cycle SC.
In this case, the potential at node N3 is first raised to H level by precharging, and then is lowered to L level in the following sense cycle SC. Accordingly, it takes a long time to lower the potential at the latter sense cycle SC. Thus, the access time is made longer and the potential at node N4 is temporarily made lower due to such a delay of access.
However, even when the potential at node N4 is changed as described above, static latch circuit 4 retains the data which is read in the former sense cycle SC so that the potential at node N5 is not changed.
Thus, it can be understood that in the third successive reading operation, there is a problem that the operation would be unstable.
The fourth successive reading operation will now be described. In this case, data at L level is read first in an initial sense cycle SC. Thereafter, in precharge cycle PC, node N3 is precharged to H level, and then data of H level is read in the following sense cycle SC.
Here, the potential at node N3 is increased so as to attain H level by precharging before it is turned to H level in the latter sense cycle SC.
As such, in the fourth successive reading operation, there is no problem caused in the access time Tac4.
As has been described above, the precharging of node N3 at the output side of the sense amplifier to the power supply potential would cause the following three problems.
The first problem is that it would cause increase in the access time as in the case of the second successive reading operation. The second problem is that the operation would be unstable as was the case in the third successive reading operation. The third problem is that there would be a lack of balance between the access times owing to the difference between the access times of the second and the fourth successive reading operations.